MC68HC11G5 Datasheet, PDF (46/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
4.9 PORT F
Port F is an 8-bit general purpose output port which also supports the external address bus.
In the expanded modes (normal expanded and test), these pins act as the low order address output
pins. During each MCU cycle, bits 0 – 7 of the address are driven out of bits 0 – 7 of Port F. When
the NHALT bit in the OPT2 register is cleared and the HALT input is pulled low, all output buffers
on Port F pins go tri-state.
In the single chip modes (normal and bootstrap), the Port F pins are general purpose output only
pins. Reading Port F in these modes returns the sensed levels at the inputs to the Port F pin drivers.
The Port F data register is cleared at reset and all Port F bits output logic zeros.
4.9.1 Data Register (PORTF)
7
6
5
4
3
2
1
0
$1005 _{PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 PORTF}
RESET:
0
0
0
0
0
0
0
0
READ: Any time (returns sensed levels at inputs of Port F pin drivers).
WRITE: Data stored in internal latch (drives pins only if configured as general purpose outputs).
RESET: In single chip modes, all Port F pins are general purpose output only pins (all zeros).
In expanded modes, all Port F pins are low order address signal outputs.
4.10 PORT G
Port G is an 8-bit bidirectional port. Port G pins serve one of two basic functions depending on the
MCU mode selected; bidirectional data lines or general purpose I/O pins. In either mode, if the
GWOM bit in the OPT2 register is set, the p-channel drivers in the output buffers are disabled (wired-
OR mode).
Port G may be programmed as an input or an output under software control. The data direction of
each pin is determined by the state of the corresponding bit in the Port G data direction register
(DDRG). A pin is configured as an output if its corresponding DDRG bit is set to a logic one; a pin
is configured as an input if its corresponding DDRG bit is cleared. At reset, all DDRG bits are cleared,
which configure all Port G pins as inputs.
During the programmed output state, a read of Port G actually reads the value of output data latch
and not the pin level. When the GWOM bit in OPT2 is set, the p-channel drivers of output buffers
are disabled (wired-OR mode).
INPUT/OUTPUT PORTS
4-8
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