MC68HC11G5 Datasheet, PDF (48/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
Bit 6 of Port H is used as the event output (EVO) or as general purpose I/O. When the EVOEN bit
in the EVCTL register is set, bit 6 of Port H becomes EVO regardless of the state of DDRH bit 6. This
does not change the state of DDRH bit 6. When the EVOEN bit in the EVCTL register is cleared,
the data direction of the pin is under the control of DDRH bit 6.
In the expanded non-multiplexed and test modes, bit 7 of Port H is used as the memory ready signal
(MRDY) or as general purpose I/O. When the MRDY bit in the OPT2 register is set, bit 7 of Port H
becomes the memory ready input regardless of the state of DDRH bit 7. When the MRDY bit in the
OPT2 register is cleared, the data direction of the pin is under the control of DDRH bit 7. In the single
chip and bootstrap modes, bit 7 of Port H is a general purpose I/O pin and the data direction of the
pin is determined by the state of DDRH bit 7.
Reading Port H reads the levels sensed at the pins regardless of the DDRH, PWENx, and EVOEN
bits. All DDRH bits are cleared at reset.
4.11.1 Data Register (PORTH)
7
$1033 _PH7
6
5
4
3
2
PH6 PH5 PH4 PH3 PH2
1
0
PH1 PH0
RESET:
0
0
0
0
0
0
0
0
Alternate Pin Function: _{MRDY EVO EVI1 EVI2 PW4 PW3 PW2 PW1}
PORTH
READ: Any time (inputs return pin levels, outputs return pin driver input levels).
WRITE: Data stored in an internal latch (drives pins only if configured for output).
RESET: General purpose high impedance inputs ($00).
4.11.2 Data Direction Register (DDRH)
$1034
RESET:
7
DDH7
0
6
DDH6
0
5
4
DDH5 DDH4
0
0
3
DDH3
0
2
DDH2
0
1
DDH1
0
0
DDH0
0
DDRH
READ: Any time
WRITE: Any time
RESET: $00 (all general purpose I/O configured for input only)
Note:
0 – Bits set to zero configure the corresponding I/O pins as inputs.
1 – Bits set to one configure the corresponding I/O pins as outputs.
The pulse width modulation timer forces the I/O state to be an output for each Port H line
associated with an enabled PWM. In such cases, the data direction bits will not be
changed but have no effect on these lines. DDRH will revert to controlling the I/O state
of a pin when the associated function is disabled. The event counter does not force the
state of any of the associated pins.
4-10
INPUT/OUTPUT PORTS
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