MC68HC11G5 Datasheet, PDF (68/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
PSEL4, PSEL3, PSEL2, PSEL1, PSEL0 — Priority Select bits 4 – 0
READ: Any time.
WRITE: Only while I bit in CCR is set (interrupts inhibited).
These five bits are used to specify one I bit related interrupt source which will become
the highest priority I bit related source (see Table 5-4).
Table 5-4. Priority Select Bits Table
PSEL4 PSEL3 PSEL2 PSEL1 PSEL0 Interrupt Source Promoted
0
0
0
X
X Reserved (Default to IRQ)
0
0
1
0
0 Reserved (Default to IRQ)
0
0
1
0
1 Reserved (Default to IRQ)
0
0
1
1
0 IRQ (External pin or Parallel I/O)
0
0
1
1
1 Real Time Interrupt
0
1
0
0
0 Timer Input Capture 1
0
1
0
0
1 Timer Input Capture 2
0
1
0
1
0 Timer Input Capture 3
0
1
0
1
1 Timer Output Compare 1
0
1
1
0
0 Timer Output Compare 2
0
1
1
0
1 Timer Output Compare 3
0
1
1
1
0 Timer Output Compare 4
0
1
1
1
1 Timer OC5/IC4
1
0
0
0
0 Timer Overflow 1
1
0
0
0
1 Pulse Accumulator Overflow
1
0
0
1
0 Pulse Accumulator Input Edge
1
0
0
1
1 SPI Serial Transfer Complete
1
0
1
0
0 SCI Serial System
1
0
1
0
1 Timer OC6/IC5
1
0
1
1
0 Timer OC7/IC6
1
0
1
1
1 Timer Overflow 2
1
1
0
0
0 Event Counter 1
1
1
0
0
1 Event Counter 2
1
1
0
1
0 Reserved (Default to IRQ)
1
1
0
1
1 Reserved (Default to IRQ)
1
1
1
X
X Reserved (Default to IRQ)
5-16
RESETS, INTERRUPTS AND LOW POWER MODES
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