MC68HC11G5 Datasheet, PDF (149/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
11.6.6 Counter Compare Registers (ECMPx)
7
6
5
4
3
2
1
0
$1076 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 ECMP1A
$1077 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 ECMP2A
$1078 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 ECMP1B
$1079 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 ECMP2B
RESET:
1
1
1
1
1
1
1
1
READ: Any time.
WRITE: Any time.
RESET: $FF.
Compare registers ECMP1A and ECMP1B are associated with counter EVCNT1. Compare
registers ECMP2A and ECMP2B are associated with counter EVCNT2.
11.7 PWM USING THE EVENT COUNTER
The PWM function of the event counter differs from the main PWM (discussed in Section 10) in that
it has no double buffered duty and period registers. This means that it is possible to generate a cycle
in which there is no duty change of state. This occurs when the duty value written is lower than the
previous value, but the counter is already past the new value. In this case the counter register will
increment all the way to the period count, roll over to $00 and count up to the new duty value before
matching. This situation can be avoided by using the event interrupts to help calculate, in software,
the correct values of duty and period to be written to the compare registers.
11.8 EFFECTIVE RANGE OF THE SET UP VALUES
In mode 0:
ECMP1A and ECMP1B: 0 to 255 ($00 to $FF)
ECMP2A and ECMP2B: 0 to 255 ($00 to $FF)
In modes 1, 2 and 3:
ECMP1A and ECMP1B: 1 to 255 ($01 to $FF)
(These values follow the boundary conditions of the PWM function.)
ECMP2A and ECMP2B: 1 to 255 to 256 ($01 to $FF to $00).
EVENT COUNTER
11-19
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