MC68HC11G5 Datasheet, PDF (94/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
Oscillator
Frequency
+4
SCP0-SCP1
Prescaler
Control
+N
SCR0-SCR2
SCI Select
Rate Control
+M
SCI
Receive
Clock (RTI)
+ 16
SCI
Transmit
Clock (Tx)
Figure 7-2. Rate Generator Division
7.3 DATA FORMAT
Receive data or transmit data is the serial data that is transferred to the internal data bus from the
receive data input pin (RXD) or from the internal bus to the transmit data output pin (TXD). The non-
return-to-zero (NRZ) data format shown in Figure 7-3 is used and must meet the following criteria:
1) The idle line is brought to a logic one state prior to transmission/reception of a character.
2) A start bit (logic zero) is used to indicate the start of a frame.
3) The data is transmitted and received least significant bit first.
4) A stop bit (logic one) is used to indicate the end of a frame. A frame consists of a start bit, a
character of eight or nine data bits, and a stop bit.
5) A break is defined as the transmission or reception of a low (logic zero) for at least one complete
frame time.
Idle Line
Control Bit "M"
Selects
8 or 9 Bit Data
012345678
0
Start
Stop Start
Figure 7-3. Data Format
7.4 RECEIVER WAKE-UP OPERATION
The MC68HC11G5 receiver logic hardware also supports a receiver wake-up function which is
intended for systems having more than one receiver. With this function a transmitting device directs
messages to an individual receiver or group of receivers by passing addressing information as the
initial byte(s) of each message. The wake-up function allows receivers not addressed to remain in
in a dormant state for the remainder of the unwanted message. This eliminates any further software
overhead to service the remaining characters of the unwanted message and thus improves system
performance.
SERIAL COMMUNICATIONS INTERFACE
7-4
For More Information On This Product,
Go to: www.freescale.com