MC68HC11G5 Datasheet, PDF (159/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
12.3.1.6
Shifts and Rotates
The shift and rotate functions in the M68HC11 CPU all involve the carry bit in the condition code
register in addition to the 8 or 16-bit operand in the instruction. This permits easy extension to
multiple word operands. Also, by setting or clearing the carry bit before a shift or rotate instruction,
the programmer can easily control what will be shifted into the opened end of an operand. The ASR
instruction maintains the original value of the most significant bit of the operand which facilitates
manipulation of twos complement (signed) numbers.
Table 12-6. Shifts and Rotates
Function
Arithmetic Shift Left Memory
Arithmetic Shift Left A
Arithmetic Shift Left B
Arithmetic Shift Left Double
Arithmetic Shift Right Memory
Arithmetic Shift Right A
Arithmetic Shift Right B
(Logical Shift Left Memory)
(Logical Shift Left A
(Logical Shift Left B
(Logical Shift Left Double
Logical Shift Right Memory
Logical Shift Right A
Logical Shift Right B
Logical Shift Right D
Rotate Left Memory
Rotate Left A
Rotate Left B
Rotate Right Memory
Rotate Right A
Rotate Right B
Mnemonic IMM DIR EXT INDX INDY INH
ASL
X
X
X
ASLA
X
ASLB
X
ASLD
X
ASR
X
X
X
ASRA
X
ASRB
X
(LSL)
X
X
X
(LSLA)
X
(LSLB)
X
(LSLD)
X
LSR
X
X
X
LSRA
X
LSRB
X
LSRD
X
ROL
X
X
X
ROLA
X
ROLB
X
ROR
X
X
X
RORA
X
RORB
X
The logical left shift instructions are shown in parenthesis because there is no difference between
an arithmetic and a logical left shift. Both mnemonics are recognized by the assembler as equivalent,
but having both instruction mnemonics makes some programs easier to read.
CPU, ADDRESSING MODES AND INSTRUCTION SET
12-9
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