MC68HC11G5 Datasheet, PDF (29/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
SECTION 3
MEMORY AND CONTROL/STATUS REGISTERS
This section describes the memory, memory subsystems mapping, and the mapping of the control
and status registers of the MC68HC11G5 MCU.
3.1 ROM
The internal 16 kilobytes of ROM occupy the highest 16k addresses in the memory map ($C000 –
$FFFF). On coming out of reset, this ROM is enabled in the single chip, test and bootstrap modes.
This ROM is disabled when the ROMON bit in the CONFIG register is clear. This register bit is only
writable in the special modes, bootstrap and test. For normal single chip mode, the ROM is on
(ROMON = 1). In expanded mode the ROM is off (ROMON = 0) thus allowing the user to execute
a program in the external memory space. (See also SECTION 3.4.5: CHANGING MODES.)
3.2 BOOTSTRAP ROM
The 256 bytes of bootstrap ROM are located at memory locations $BF00 – $BFFF. The reset and
interrupt vectors, while in this mode, are addressed at $BFC0 – $BFFF. The interrupt vectors point
to pseudo-vectors located in RAM (see Section 2.1.3 and Table 2-2).
3.3 RAM
Using the INIT control register, the 512 byte block of static RAM is mappable to the start of any 4
kilobyte boundary in memory. The reset default position of the RAM is located at $0000 to $01FF.
If the internal registers are mapped in the same 4 kilobyte block as RAM, the registers will have
higher priority.
The RAM is implemented with static cells and retains its contents during WAIT, HALT and STOP
modes. The contents of the RAM can also be retained during power-down, by supplying a low
current back-up power source to the Vkam pin (MODB).
MEMORY AND CONTROL/STATUS REGISTERS
3-1
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