MC68HC11G5 Datasheet, PDF (22/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
2.1.4.1 Factory Test Register (TEST1)
7
6
5
4
3
2
1
0
$103E TILOP TPWSL OCCR CBYP1 DISR FCM FCOP CBYP2 TEST1
RESET:
0
0
0
0
0
0
0
0
READ: Any time (always zero if not in a test mode)
WRITE: Only while SMOD = 1 (TEST or BOOT modes)
TILOP — Test Illegal Opcode
0 – Normal operation (trap on illegal opcodes)
1 – Stop giving LIR when an illegal opcode is found
This test mode allows testing of all illegal opcodes serially without servicing an
interrupt after each illegal opcode is received. LIR (inactive for illegal opcodes) is
used to monitor correct CPU operation.
TPWSL — Pulse Width Modulation Scaled Clock
0 – Normal operation
1 – Clock S (Scaled) from the PWM timer is output to and readable on the PWSCAL
register. Normal writing of the PWSCAL register will still function.
OCCR — Output Condition Code Register Status to Timer Port
0 – Normal operation
1 – The Condition Code bits H, N, Z, V, and C are driven out of the 5 most significant
bits (bits 3 – 7, respectively) of the timer I/O port to allow the test system to
monitor CPU operation.
CBYP1 — Timer Counter 1 Divider Chain By-pass
0 – Normal operation
1 – 16-bit free running timer counter 1 is divided into 8-bit halves and the prescaler is
by-passed. The system E-clock drives both halves directly.
DISR — Disable Resets from COP and Clock Monitor
0 – Normal operation
1 – Regardless of other control bit states, COP and clock monitor will not generate a
system reset.
When the device is reset in test or bootstrap mode (SMOD = 1), the DISR bit is initialized
to 1 so that resets from the COP and clock monitor are disabled. When reset in normal
modes, the DISR bit is initialized to 0.
FCM — Force Clock Monitor Failure
0 – Normal operation
1 – Immediately generates a Clock Monitor failure reset. Note that the CME bit must
also be set for the reset to be forced.
OPERATING MODES AND SIGNAL DESCRIPTION
2-4
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