MC68HC11G5 Datasheet, PDF (183/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
13.9 EXPANSION BUS TIMING
(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH unless otherwise noted)
Num
Characteristic
Symbol Min Max Unit
Frequency of Operation (E-Clock)
1 Cycle Time
fo
—
2.1 MHz
tcyc
476
—
ns
2 Pulse Width E Low (1/2 tcyc - 23ns)
3 Pulse Width E High (1/2 tcyc - 28ns)
4 E Rise and Fall Time
9 Address Hold Time (tAH = 1/8 t _cyc - 29.5ns)
(See Note 1(A))
t _ELEH 215
—
ns
t _EHEL 210
—
ns
tR, tF
—
20
ns
tAH
30
—
ns
12 Address Valid Time to E Rise (See Note 1(B))
17 Read Data Setup Time
18 Read Data Hold Time
19 Write Data Delay Time
21 Write Data Hold Time
tAV
120
—
ns
tDSR
30
—
ns
tDHR
10
—
ns
tDDW
—
80
ns
tDHW 50
—
ns
29 MPU Address Access Time
tACCA 320
—
ns
(tACCA = tAV + tR + t _EHEL - tDSR _{(See Note 1(A))}
NOTES:
1. Input clock with duty cycle other than 50% will affect the bus performance. Timing parameters
affected by the input clock duty cycle are identified by (A) and (B). To re-calculate approximate
bus timing values, substitute the following expressions in place of 1/8 t _cyc in the above formulae
where applicable:
(A) (1-DC) x 1/4 t _cyc
(B) DC x 1/4 t _cyc
where DC is the decimal value of duty cycle percentage (High time).
2. All timing is shown with respect to 20% V _DD and 70% VDD.
ELECTRICAL SPECIFICATIONS
For More Information On This Product,
Go to: www.freescale.com
13-17