MC68HC11G5 Datasheet, PDF (42/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
Note:
The timer forces each Port A line associated with an enabled output compare to be an
output. In such cases the data direction bits will not be changed but will have no effect
on these lines. DDRA will revert to controlling the I/O state of a pin when the associated
timer output compare is disabled.
4.5 PORT B
Port B is an 8-bit general purpose output port which also supports the external address bus.
In the expanded modes (normal expanded and test), these pins act as the high order address output
pins. During each MCU cycle, bits 8 through 15 of the address are driven out of bits 0 through 7 of
Port B. When the NHALT bit in the OPT2 register is cleared and the HALT input is pulled low, all
output buffers of Port B bits go tri-state.
In the single chip modes (normal and bootstrap), the Port B pins are general purpose output only
pins. Reading Port B in these modes returns the sensed levels at the inputs to the Port B pin drivers.
The Port B data register is cleared at reset and all Port B bits output logic zeros.
4.5.1 Data Register (PORTB)
7
6
5
4
3
2
1
0
$1004 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PORTB
RESET:
0
0
0
0
0
0
0
0
Alternate Pin Function: A15 A14 A13 A12 A11 A10 A9
A8
READ: Any time (returns levels sensed at inputs of Port B pin drivers).
WRITE: Data stored in internal latch (drives pins only if configured as general purpose outputs).
RESET: In single chip modes, all Port B pins are general purpose output only pins (all zeros).
In expanded modes, all Port B pins are high order address signal outputs.
4.6 PORT C
Port C is an 8-bit bidirectional port. Port C pins serve one of two basic functions depending on the
MCU mode selected; bidirectional data lines or general purpose I/O pins. In either mode, if the
CWOM bit in the OPT2 register is set, the p-channel drivers in the output buffers are disabled (wired-
OR mode).
In the expanded modes (normal expanded and test), these pins act as bidirectional data pins.
During the CPU read cycle, data on the Port C pins are latched internally on the falling edge of E.
During the CPU write cycle, the internal data is driven out of Port C and is valid at the falling edge
of E. During an internal address read cycle with the IRV bit in the OPT2 register set, the internal data
is also driven out of Port C and is valid at the falling edge of E. If the MCU is in the Halt state, all Port
C bits become tri-state.
INPUT/OUTPUT PORTS
4-4
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