MC68HC11G5 Datasheet, PDF (55/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
Special considerations are needed when using STOP and the clock monitor in the same system.
Since the STOP function causes the clocks to be halted, the clock monitor function will generate a
reset sequence if it is enabled prior to the STOP mode being entered. For systems which do not
expect or want a STOP function, this interaction can be useful to detect the unauthorized execution
of a STOP instruction which could not be detected by the COP watchdog system. On the other hand,
in systems which utilise both the STOP and clock monitor functions, this interaction means that the
CME bit must be written to zero just prior to executing a STOP instruction and should be written back
to one as soon as the MCU resumes execution.
5.1.5 Configuration Options Register (OPTION)
The bits in this register control certain configuration options, most of which can be changed only
during the first 64 cycles after reset in normal operating modes.
7
6
5
4
3
2
1
0
$1039 ADPU CSEL IRQE DLY CME
0
CR1 CR0 OPTION
RESET:
0
0
0
1
0
0
0
0
READ: Any time.
WRITE:
Bits 3, 6, and 7 may be written at any time.
Bits 0, 1, 4, and 5 may be written once only in the normal operating modes, and only
during the first 64 cycles after reset. After this time the bits are read-only in the normal
operating modes (SMOD = 0). In the special test and bootstrap modes (SMOD = 1),
writes are always permitted.
RESET: $10.
ADPU — A/D Power Up
0 – A/D system powered down to save supply current.
1 – A/D system powered up (allow about 100 µs for stabilization).
CSEL — Clock Select
This bit should be set to one if the E-clock is less than 1 MHz.
0 – A/D uses the system E-clock (must be 1.0 MHz or greater).
1 – A/D uses an internal R-C clock source (about 1.5 MHz).
IRQE — IRQ Select Edge Sensitive Only
0 – IRQ configured for low level recognition.
1 – IRQ configured to respond only to falling edges.
DLY — Enable Oscillator Start-up delay on exit from STOP
0 – No stabilization delay imposed on exit from STOP mode.
1 – A stabilization delay is imposed before processing resumes after STOP.
This bit is set during reset and controls whether or not a relatively long stabilization delay
is imposed before processing can resume after a STOP period. If an external clock signal
RESETS, INTERRUPTS AND LOW POWER MODES
5-3
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