MC68HC11G5 Datasheet, PDF (76/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
the counter to be preset to $FFF8 regardless of the data written. This preset capability is intended
only for factory testing.
Because its width is 16 bits, the value in the free running counter repeats every 65,536 counts
(prescaler timeouts). When the count changes from $FFFF to $0000 the timer overflow flag bit
(TOxF), in the TFLG2 register, is set. A timer overflow interrupt can be enabled by setting its interrupt
enable bit (TOxI), in the TMSK2 register.
6.4.2 Prescaler Register (TPRE)
7
6
5
4
3
$1058 TEDGB TEDGA PR2B PR2A 0
RESET:
0
0
0
0
0
2
1
0
0 PR1B PR1A TPRE
0
0
0
READ: Any time.
WRITE: If SMOD = 0, may be written only once during the first 64 cycles. After this time, the bits
become read-only. If SMOD = 1, writing is always permitted.
TEDGB, TEDGA — Timer External Clock Edge Select
These two bits determine which edge(s) of the external clock will cause timer counter 2
to increment. The external clock comes in via Port J, bit 0.
TEDGB
0
0
1
1
TEDGA
0
1
0
1
Configuration
Counter 2 uses the internal clock and
prescaler
Count on rising edges only
Count on falling edges only
Count on any edge (rising or falling)
Note:
the maximum frequency of the input clock must be less than E/2 when counting on
only rising or falling edges and must be less than E/4 when counting on both edges.
PROGRAMMABLE TIMER
6-6
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