MC68HC11G5 Datasheet, PDF (185/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
13.10 SERIAL PERIPHERAL INTERFACE (SPI) TIMING
(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH unless otherwise noted)
Num
Characteristic
Symbol Min
Operating Frequency
1 Cycle Time
Master fop(m)
dc
Slave fop(s)
dc
Master tcyc(m)
2.0
Slave tcyc(s)
480
2 Enable Lead Time
3 Enable Lag Time
4 Clock (SCK) High Time
Master tlead(m)
*
Slave tlead(s) 240
Master tlag(m)
*
Slave tlag(s)
240
Master tw(SCKH)m 340
Slave tw(SCKH)s 190
5 Clock (SCK) Low Time
6 Data Setup Time
Master tw(SCKL)m 340
Slave tw(SCKL)s 190
Master tsu(m)
100
Slave tsu(s)
100
7 Data Hold Time
8 Access Time
(Time to Data Active from High-Impedance State)
9 Disable Time
(Hold Time to High-Impedance State)
Master th(m)
100
Slave th(s)
100
Slave
ta
0
Slave
tdis
—
10 Data Valid (After Enable Edge)**
tv(s)
—
11 Data Hold Time (Outputs) (After Enable Edge)
tho
- 40
12 Rise Time (20% V _DD to 70% VDD, CL = 200pF)
SPI Outputs (SCK, MOSI, MISO)
SPI Inputs (SCK, MOSI, MISO, SS)
13 Fall Time (70% V _DD to 20% VDD, CL = 200pF)
SPI Outputs (SCK, MOSI, MISO)
SPI Inputs (SCK, MOSI, MISO, SS)
tr(m)
—
tr(s)
—
tf(m)
—
tf(s)
—
NOTES:
* Signal production depends on software.
** Assumes 200 pF load on all SPI pins.
1. All timing is shown with respect to 20% V _DD and 70% VDD unless otherwise noted.
Max
0.5
2.1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
120
240
240
—
100
2.0
100
2.0
Unit
fo
MHz
tcyc
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
µs
ELECTRICAL SPECIFICATIONS
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13-19