MC68HC11G5 Datasheet, PDF (132/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
Mode 0: Pulse Accumulator modifies PWM output
by adding offset and controlling the clearing
* _INPUT2
of the PWM
PA
* _{INPUT1 q PWM}
OUTPUT
Mode 1: PA and PWM are completely independent
* _INPUT2
* _INPUT1
PA
PWM
OUTPUT
Mode 2: PA Counts the PWM periods (which may
be of variable duration and modulation)
* _INPUT2
* _INPUT1
PA
PWM
OUTPUT
Mode 4: PA acts as programmable 8-bit prescaler
for PWM unit
* _INPUT2
PA
* _INPUT1
PWM
OUTPUT
* ^{INPUT1 and INPUT2 can be driven from the E-clock, a second value of the E-clock or from}
external signals on the EVI2 and EVI1 input pins. When EVI2 or EVI1 is not being used for
this purpose they may be used as general I/O pins (PH4 and PH5).
Figure 11-1. Event Counter Operating Modes
Each unit can generate an interrupt signal (referred to as EVENT1 or EVENT2 in the following
discussion) on a counter match with one of its two compare registers.
The PWM unit is comprised of counter 1 (EVCNT1), two compare registers (ECMP1A and
ECMP1B), an input selector (INPUT1) and an output selector. The PA unit is comprised of Counter
2 (EVCNT2), two compare registers (ECMP2A and ECMP2B) and an input selector (INPUT2).
11-2
EVENT COUNTER
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