MC68HC11G5 Datasheet, PDF (47/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
4.10.1 Data Register (PORTG)
7
$1002 _PG7
RESET:
0
6
5
4
3
2
PG6 PG5 PG4 PG3 PG2
0
0
0
0
0
1
0
PG1 PG0
0
0
PORTG
READ: Any time (inputs return pin levels; outputs return pin driver input levels).
WRITE: Data stored in an internal latch (drives pins only if configured as outputs).
RESET: General purpose high impedance inputs ($00)
4.10.2 Data Direction Register (DDRG)
$1003
RESET:
7
6
5
4
DDG7 DDG6 DDG5 DDG4
0
0
0
0
3
2
1
0
DDG3 DDG2 DDG1 DDG0
0
0
0
0
DDRG
READ: Any time.
WRITE: Any time.
RESET: $00 (all general purpose I/O configured for input only).
0 – Bits set to zero configure the corresponding I/O pins as inputs.
1 – Bits set to one configure the corresponding I/O pins as outputs.
4.11 PORT H
Port H is an 8-bit general purpose I/O port. Three of the pins are used for the event counter (see
SECTION 11: EVENT COUNTER). Four of the remaining pins are used for the 4-channel PWM
timer (see SECTION 10: PULSE WIDTH MODULATION TIMER). The remaining pin is used for the
memory ready input signal (MRDY). Any pins not used for these functions may be used as general
purpose I/O.
When the PWENx bit in the PWEN register is set, the associated Port H bit is forced to be a PWM
output regardless of the state of the DDRH bit. This does not change the state of the DDRH bit. When
the PWENx bit in the PWEN register is cleared, the pin defaults to being a general purpose I/O. The
data direction of the pin is determined by the state of the corresponding DDRH bit.
Bits 4 and 5 of Port H are used as the EVI2 and EVI1 inputs or as general purpose I/O. The data
direction of Port H bits 4 and 5 is always under the control of DDRH bits 4 and 5, whether EVI2 and
EVI1 are enabled or not. If the pin is configured as an output by its DDRH bit, the output data of the
Port H register is also the input data of the event counter.
INPUT/OUTPUT PORTS
4-9
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