MC68HC11G5 Datasheet, PDF (87/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
TO2I — Timer Overflow 2 Interrupt Enable
0 – Interrupt inhibited
1 – Hardware interrupt requested when TO2F flag set
5/6I — Input Capture 5/Output Compare 6 Interrupt Enable
0 – Interrupt inhibited
1 – Hardware interrupt requested when 5/6F flag set
6/7I — Input Capture 6/Output Compare 7 Interrupt Enable
0 – Interrupt inhibited
1 – Hardware interrupt requested when 6/7F flag set
6.4.18 Miscellaneous Timer Interrupt Flag Register 2 (TFLG2)
The miscellaneous timer system flag register (TFLG2) contains flag bits which are set by hardware
when the corresponding timer interrupt condition occurs. Any flag bits in the TFLG1 register which
are set will remain set until they are cleared by writing ones to those bits.
7
6
5
4
3
2
1
0
$1025 TO1F RTIF PAOVF PAIF TO2F 5/6F 6/7F
0
TFLG2
RESET:
0
0
0
0
0
0
0
0
READ: Any time.
WRITE: Used in clearing mechanism (see above).
RESET: $00
TO1F — Timer Overflow 1 Flag
Set when 16-bit free running timer 1 overflows from $FFFF to $0000. This bit is cleared
by writing to the TFLG2 register with bit 7 set.
RTIF — Real Time (Periodic) Interrupt Flag
Set when the tap point selected becomes set. This bit is cleared by writing to the
TFLG2 register with bit 6 set.
PAOVF — Pulse Accumulator Overflow Flag
Set when the 8-bit pulse accumulator overflows from $FF to $00. This bit is cleared
by writing to the TFLG2 register with bit 5 set.
PROGRAMMABLE TIMER
6-17
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