MC68HC11G5 Datasheet, PDF (51/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
4.13.2 Memory Ready (MRDY)
A memory ready function is available on the MC68HC11G5. This allows interfacing to slow
peripherals and dual ported RAM, and to dynamic RAM without a hidden refresh.
When the memory ready function is enabled, MRDY is used to stretch the CPU timing and E-clock
to allow a longer access time. Note that internal clocks to timers and baud rate generators continue
to run at the normal rate so that the timer and serial systems are not affected.
Port H bit 7 is used as the memory ready line (MRDY). When this line is low, an external access will
be stretched until the line goes high. During the stretch time the address lines will be held and
E will be kept in the high state. For write operations the data will be held and for read operations the
data bus lines will be inputs. When MRDY goes high, E will fall thus ending the cycle, and
will continue at a normal rate until the next external access during which MRDY is low. Note that the
bus will only stretch for integral numbers of E-clock cycles.
4.13.3 Options Register 2 (OPT2)
7
6
5
4
3
$1038 GWOM CWOM 0
IRV
0
RESET:
0
0
0
—
0
2
1
0
0 MRDY NHALT OPT2
0
0
1
GWOM — PORT G Wired-Or Mode
READ: Any time.
WRITE: Any time.
0 – Port G operates normally.
1 – Port G outputs are open drain (used to facilitate testing).
CWOM — PORT C Wired-Or Mode
READ: Any time.
WRITE: Any time.
0 – Port C operates normally.
1 – Port C outputs are open drain (used to facilitate testing).
INPUT/OUTPUT PORTS
4-13
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