MC68HC11G5 Datasheet, PDF (129/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
PPOL3 — Pulse Width Channel 3 Polarity
1 – PWM channel 3 output is high at the beginning of the clock cycle, then goes low
when the duty count is reached.
0 – PWM channel 3 output is low at the beginning of the clock cycle, then goes high
when the duty count is reached.
PPOL2 — Pulse Width Channel 2 Polarity
1 – PWM channel 2 output is high at the beginning of the clock cycle, then goes low
when the duty count is reached.
0 – PWM channel 2 output is low at the beginning of the clock cycle, then goes high
when the duty count is reached.
PPOL1 — Pulse Width Channel 1 Polarity
1 – PWM channel 1 output is high at the beginning of the clock cycle, then goes low
when the duty count is reached.
0 – PWM channel 1 output is low at the beginning of the clock cycle, then goes high
when the duty count is reached.
10.5.6 Scale Register (PWSCAL)
7
6
5
4
3
2
1
0
$1062 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 PWSCAL
RESET:
0
0
0
0
0
0
0
0
READ: Any time.
WRITE: Any time (causes clock counter to be reset to $00).
RESET: $00
Each of the PWM channels can select clock S (scaled) as its input clock. Clock S may be selected
for channel x by writing a one to the control bit PCLKx. Clock S is generated by taking clock A,
dividing it by the value in this PWSCAL register and dividing that by two. When PWSCAL = $00, clock
A is divided by 256 then divided by two to generate clock S. In test mode, the PWSCAL register can
be used to read the value of clock S (scaled) if the TPWSL bit in the TEST1 register is set.
PULSE WIDTH MODULATION TIMER
10-9
For More Information On This Product,
Go to: www.freescale.com