MC68HC11G5 Datasheet, PDF (86/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
OC1F, OC2F,OC3F, OC4F — Output Compare “x” Flag
Set when the 16-bit timer counter register matches the OCx compare register. These bits
are cleared by writing to the TFLG1 register with the corresponding bits (4–7) set.
4/5F — Input Capture 4/Output Compare 5 Flag
Set when an input capture occurs on IC4 or an output compare occurs on OC5. This bit
is cleared by writing to the TFLG1 register with bit 3 set.
IC1F, IC2F, IC3F — Input Capture “x” Flag
Set when an input capture occurs on ICx. These bits are cleared by writing to the TFLG1
register with the corresponding bits (0–2) set.
6.4.17 Miscellaneous Timer Interrupt Mask Register 2 (TMSK2)
The bits in TMSK2 correspond bit-for-bit with the bits in the TFLG2 status register. A zero inhibits
the corresponding flag from causing a hardware interrupt. A one enables the corresponding flag to
cause a hardware interrupt.
7
6
5
4
3
2
1
$1024 TO1I RTII PAOVI PAII TO2I 5/6I 6/7I
RESET:
0
0
0
0
0
0
0
0
0
TMSK2
0
READ: Any time.
WRITE: Any time.
RESET: $00
TO1I — Timer Overflow 1 Interrupt Enable
0 – Interrupt inhibited.
1 – Hardware interrupt requested when TO1F flag set.
RTII — RTI Interrupt Enable
0 – Interrupt inhibited.
1 – Hardware interrupt requested when RTIF flag set.
PAOVI — Pulse Accumulator Overflow Interrupt Enable
0 – Interrupt inhibited
1 – Hardware interrupt requested when PAOVF flag set
PAII — Pulse Accumulator Input Interrupt Enable
0 – Interrupt inhibited
1 – Hardware interrupt requested when PAIF flag set
6-16
PROGRAMMABLE TIMER
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