MC68HC11G5 Datasheet, PDF (142/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
11.5 MODE 3: 8-BIT PWM WITH 256 CLOCK PRESCALER
In mode 3, the event counter operates as an 8-bit PWM unit with a software programmable 8-bit
clock prescaler (the PA unit). If mode 3 (EVMDB = 1, EVMDA = 1) is selected then the elements of
the event counter are configured as shown in Figure 11-5.
The only difference between this mode and mode 1 lies in the clock source used to drive the counter
in the PWM unit (EVCNT1). In mode 1, the clock signal comes via the INPUT2 selector and is either
derived from the E-clock (gated or ungated) or an external signal. In mode 3, the signal which results
from a successful comparison between EVCNT2 and ECMP2A in the PA unit is used to drive
EVCNT1 in the PWM unit. EVCNT1, therefore, increments by one every time the value in EVCNT2
reaches the value programmed into ECMP2A. In other words, the PA unit acts as a prescaler to the
PWM unit, its division ratio being the 8-bit value in ECMP2A.
11.5.1 Operation of Pulse Width Modulation Unit in Mode 3
The PWM unit is clocked each time there is a successful comparison between EVCNT2 and
ECMP2A in the PA unit, i.e. at the end of each PA counting period.
The period of the PWM output signal is stored in ECMP1A. When a match occurs between this
compare register and the counter register, EVCNT1, the output unit EVO is reset and EVCNT1 is
cleared (to zero). At the same time, an interrupt signal EVENT1 is generated which, if enabled,
interrupts the CPU.
The duty cycle of the PWM output signal is stored in ECMP1B. When a match occurs between this
compare register and EVCNT1, the PWM output signal changes state (from zero to one or from one
to zero depending on the polarity selected by the output unit.
11-12
EVENT COUNTER
For More Information On This Product,
Go to: www.freescale.com