MC68HC11G5 Datasheet, PDF (85/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
6.4.15 Main Timer Interrupt Mask Register 1 (TMSK1)
The bits in TMSK1 correspond bit-for-bit with the bits in the TFLG1 status register. A zero disables
the corresponding flag from causing a hardware interrupt. A one enables the corresponding flag to
cause a hardware interrupt.
7
6
5
4
3
2
1
0
$1022 OC1I OC2I OC3I OC4I 4/5I IC1I IC2I IC3I TMSK1
RESET:
0
0
0
0
0
0
0
0
READ: Any time
WRITE: Any time
RESET $00
OC1I, OC2I, OC3I, OC4I — Output Compare “x” Interrupt Enable
0 – Interrupt inhibited.
1 – OCx interrupt requested when OCxF flag set
4/5I — Input Capture 4/Output Compare 5 Interrupt Enable
0 – Interrupt inhibited.
1 – IC4 or OC5 interrupt requested when 4/5F flag set
IC1I, IC2I, IC3I — Input Capture “x” Interrupt Enable
0 – Interrupt inhibited.
1 – ICx interrupt requested when ICxF flag set
6.4.16 Main Timer Interrupt Flag Register 1 (TFLG1)
The main timer system flag register (TFLG1) contains flag bits which are set by hardware when the
corresponding timer interrupt condition occurs. Any flag bits in the TFLG1 register which are set will
remain set until they are cleared by writing ones to those bits.
7
6
5
4
3
2
1
0
$1023 OC1F OC2F OC3F OC4F 4/5F IC1F IC2F IC3F TFLG1
RESET:
0
0
0
0
0
0
0
0
READ: Any time.
WRITE: Used in clearing mechanism (writing ones to bits set cause these bits to be
cleared).
RESET: $00
PROGRAMMABLE TIMER
6-15
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