MC68HC11G5 Datasheet, PDF (110/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
When the SPE bit is set the Port D bit 2, 3, 4, and 5 pins are dedicated to the SPI function.
If the SPI is in master mode and DDRD bit 5 is set, then the Port D bit 5 pin becomes a
general purpose output instead of the SS input.
DWOM — Port D Wired-OR Mode
0 – Port D output buffers operate normally (CMOS outputs).
1 – Port D output buffers operate as open-drain outputs.
DWOM affects all six Port D pins together.
MSTR — Master/Slave Mode Select
0 – Slave mode.
1 – Master mode.
CPOL — Clock Polarity
When the clock polarity bit is cleared and data is not being transferred, a steady state low
value is produced at the SCK pin of the master device. Conversely, if this bit is set,
the SCK pin will idle high. This bit is also used in conjunction with the clock phase
control bit to produce the desired clock-data relationship between master and slave. See
Figure 8-1.
CPHA — Clock Phase
The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relationship
between master and slave. The CPOL bit can be thought of simply as inserting an inverter
in series with the SCK line. The CPHA bit selects one of two fundamentally different
clocking protocols. When CPHA = 0, the shift clock is the logical OR of SCK and SS. As
soon as SS goes low, the transaction begins and the first edge on SCK invokes the first
data sample. When CPHA = 1, the SS pin may be thought of as a simple output enable
control. Refer to Figure 8-1.
SPR1, SPR0 — SPI Clock (SCK) Rate Select Bits
If the device is a master, the two serial peripheral rate bits select one of four division ratios
of the E-clock to be used as SCK (see Table 8-1). These bits have no effect in slave mode.
Table 8-1. SPI Rate Selection
SPR1
0
0
1
1
Internal Processor
SPR0 _{Clock Divide By}
0
2
1
4
0
16
1
32
SERIAL PERIPHERAL INTERFACE
8-6
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