MC68HC11G5 Datasheet, PDF (128/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
10.5.5 Polarity Select Register (PWPOL)
Each channel has a polarity bit (PPOLx) to start the cycle with a high signal or with a low signal. This
is shown on the block diagram as a multiplex select of either the Q output or the Q output of the PWM
output flip-flop. When one of the bits in the PWPOL register is set, the associated PWM channel
output is high at the beginning of the clock cycle, then goes low when the duty count is reached.
7
6
5
4
3
2
1
0
$1061 PCLK4 PCLK3 PCLK2 PCLK1 PPOL4 PPOL3 PPOL2 PPOL1 PWPOL
RESET:
0
0
0
0
0
0
0
0
READ: Any time.
WRITE: Any time.
RESET: $00
PCLK4 — Pulse Width Channel 4 Clock Select
1 – The clock source for PWM channel 4 is Clock S. (Clock S equals Clock A divided
by two times the value (plus one) in the PWSCAL register.)
0 – Clock B is the clock source for PWM channel 4.
PCLK3 — Pulse Width Channel 3 Clock Select
1 – The clock source for PWM channel 3 is Clock S.
0 – Clock B is the clock source for PWM channel 3.
PCLK2 — Pulse Width Channel 2 Clock Select
1 – The clock source for PWM channel 2 is Clock S.
0 – Clock A is the clock source for PWM channel 2.
PCLK1 — Pulse Width Channel 1 Clock Select
1 – The clock source for PWM channel 1 is Clock S.
0 – Clock A is the clock source for PWM channel 1.
Note:
While register bits PCLK1 – 4 may be written at any time, if a clock select is changed while
a PWM signal is being generated, a truncated pulse may occur during the transition.
PPOL4 — Pulse Width Channel 4 Polarity
1 – PWM channel 4 output is high at the beginning of the clock cycle, then goes low
when the duty count is reached.
0 – PWM channel 4 output is low at the beginning of the clock cycle, then goes high
when the duty count is reached.
10-8
PULSE WIDTH MODULATION TIMER
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