MC68HC11G5 Datasheet, PDF (82/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
6.4.11 Control Register 1 (TCTL1)
7
6
5
4
3
2
1
0
$1020 OM2 OL2 OM3 OL3 OM4 OL4 OM5 OL5 TCTL1
RESET:
0
0
0
0
0
0
0
0
READ: Any time.
WRITE: Any time.
RESET: $00
OMx — Output Mode; OLx — Output Level
These four pairs of control bits are encoded to specify the output action to be taken as
a result of a successful OCx compare (OC2 – OC5). When either OMx or OLx is set, the
pin associated with OCx becomes an output tied to OCx regardless of the state of the
associated DDR bit. Output compare OC5 only functions if the TO5I4 register is
programmed for output compare OC5 operation via the I4/O5 bit in the PACTL register.
OMx
OLx
0
0
0
1
1
0
1
1
Action taken upon successful compare
Timer disconnected from output pin logic
Toggle OCx output line
Clear OCx output line to zero
Set OCx output line to one
6.4.12 Timer Control Register 2 (TCTL2)
7
6
5
4
3
2
1
0
$1021 EDG4B EDG4A EDG1B EDG1A EDG2B EDG2A EDG3B EDG3A TCTL2
RESET:
0
0
0
0
0
0
0
0
READ: Any time
WRITE: Any time
RESET: $00
EDGxB, EDGxA — Input Capture Edge Control
The level transition which triggers counter transfer is defined by the corresponding
input edge bits (EDGxB, EDGxA). These bit pairs are encoded to configure input
captures IC1 – IC4 to occur on rising edges, falling edges, either edge, or to inhibit
capture. Input capture 4 only functions if the TO5I4 register is programmed for input
capture IC4 operation by the I4/O5 bit in the PACTL register.
6-12
PROGRAMMABLE TIMER
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