MC68HC11G5 Datasheet, PDF (130/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
10.5.7 Enable Register (PWEN)
Each timer has an enable bit (PWENx) to start its waveform output. Writing any of these PWENx
bits to one causes the associated Port H line to become an output regardless of the state of the
associated DDR bit. This does not change the state of the DDR bit and, when PWENx returns to
zero, the DDR bit again controls the I/O state. On the front end of the PWM timer the clock is enabled
to the PWM circuit by the PWENx enable bit being high. A synchronizing circuit guarantees that the
clock will only be enabled or disabled at an edge.
7
6
5
4
3
2
1
0
$1063
0
0
0
0 PWEN4 PWEN3 PWEN2 PWEN1 PWEN
RESET:
0
0
0
0
0
0
0
0
READ: Any time.
WRITE: Any time.
RESET: $00.
PWEN4 — Pulse Width Channel 4 Enable
1 – PWM channel 4 is enabled. The pulse modulated signal becomes available at
Port H bit 3 when its clock source begins its next cycle.
0 – PWM channel 4 is disabled.
PWEN3 — Pulse Width Channel 3 Enable
1 – PWM channel 3 is enabled. The pulse modulated signal becomes available at
Port H bit 2 when its clock source begins its next cycle.
0 – PWM channel 3 is disabled.
PWEN2 — Pulse Width Channel 2 Enable
1 – PWM channel 2 is enabled. The pulse modulated signal becomes available at
Port H bit 1 when its clock source begins its next cycle.
0 – PWM channel 2 is disabled.
PWEN1 — Pulse Width Channel 1 Enable
1 – PWM channel 1 is enabled. The pulse modulated signal becomes available at
Port H bit 0 when its clock source begins its next cycle.
0 – PWM channel 1 is disabled.
10-10
PULSE WIDTH MODULATION TIMER
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