MC68HC11G5 Datasheet, PDF (109/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
Master
8-bit Shift Register
MISO
MOSI
MISO
MOSI
SPI Clock Generator
SCK
SCK
SS ^+5V SS
Slave
8-bit Shift Register
Figure 8-3. Serial Peripheral Interface Master-Slave Interconnection
Due to data direction register control of SPI outputs and the Port D wire-OR mode (DWOM) option,
the SPI system can be configured in a variety of ways. Systems with a single bidirectional data path
rather than separate MISO and MOSI paths can be accommodated. Since MC68HC11G5 slaves
can selectively disable their MISO output, a broadcast message protocol is also possible.
8.4 SPI REGISTERS
There are three registers in the serial peripheral interface which provide control, status and data
storage functions. These registers are called the serial peripheral control register (SPCR), the serial
peripheral status register (SPSR) and the serial peripheral data I/O register (SPDAT).
8.4.1 Control Register (SPCR)
7
$1028 SPIE
RESET:
0
6
5
4
3
2
1
0
SPE DWOM MSTR CPOL CPHA SPR1 SPR0
0
0
0
0
1
U
U
SPCR
READ: Any time
WRITE: Any time.
SPIE — SPI Interrupt Enable
0 – SPI interrupts disabled.
1 – SPI interrupts enabled.
When this bit is set to one, a hardware interrupt sequence is requested each time the
SPIF or MODF status flag is set. SPI interrupts are inhibited if this bit is clear or if the I
bit in the CC Register is set.
SPE — SPI System Enable
0 – SPI system off.
1 – SPI system on.
SERIAL PERIPHERAL INTERFACE
8-5
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