MC68HC11G5 Datasheet, PDF (60/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
SP
SP – 1
SP – 2
SP – 3
SP – 4
SP – 5
SP – 6
SP – 7
SP – 8
SP – 9
STACK
PCL
PCH
IYL
IYH
IXL
IXH
ACCA
ACCB
CCR
– SP Before Interrupt
– SP After Interrupt
Figure 5-1. Interrupt Stacking Order
5.2.2 Software Interrupt (SWI)
SWI is an instruction rather than a prioritized asynchronous interrupt source. It is non-maskable. In
one sense it is lower in priority than any source, because once an interrupt sequence has begun,
SWI cannot override it. In another sense, it is higher in priority than any source except reset, because
once the SWI opcode is fetched, no other source can be serviced until after the first instruction in
the SWI service routine has been executed. SWI causes the I mask bit in the CCR to be set.
5.2.3 Illegal Opcode Trap
Since not all possible opcodes or opcode sequences are defined, an illegal opcode detection circuit
has been included in the MC68HC11G5. When an illegal opcode is detected, an interrupt is
requested to the illegal opcode vector. It is non-maskable and the illegal opcode vector should never
be left uninitialized.
5.2.4 Real Time Interrupt
The real time interrupt (or periodic interrupt) feature on the MC68HC11G5 is configured and
controlled by three bits in the PACTL register (RTR2, RTR1 and RTR0 which select one of six
interrupt rates based on the MCU E-clock), an interrupt status flag (RTIF) in the TFLG2 register, and
a mask bit (RTII) in the TMSK2 register (which enables/inhibits hardware interrupts based on the
RTIF flag bit). After reset, one entire real time interrupt period will elapse before the RTIF flag gets
set for the first time. (See SECTION 6: PROGRAMMABLE TIMER, REAL TIME INTERRUPT AND
PULSE ACCUMULATOR for more information on the real time interrupt.)
RESETS, INTERRUPTS AND LOW POWER MODES
5-8
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