MC68HC11G5 Datasheet, PDF (148/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
EV2I — Event 2 Interrupt Enable
0 – Interrupt inhibited.
1 – Hardware interrupt requested when EV2F flag set.
EV1I — Event 1 Interrupt Enable
0 – Interrupt inhibited.
1 – Hardware interrupt requested when EV1F flag set.
11.6.4 Interrupt Flag Register (EVFLG)
7
6
5
4
3
2
1
0
$1073
EV2F EV1F EVFLG
RESET:
0
0
0
0
0
0
0
0
READ: Any time.
WRITE: Used as clearing mechanism (bits set cause corresponding bits to be cleared).
RESET: $00.
EV2F — Event Interrupt 2 Flag
Set by a successful match of EVCNT2 and ECMP2B. This bit is cleared automatically by
a write to the EVFLG register with bit 1 set.
EV1F — Event interrupt 1 Flag
Set by a successful match of EVCNT1 and ECMP1A. This bit is cleared automatically by
a write to the EVFLG register with bit 0 set.
11.6.5 Counter Registers (EVCNTx)
7
6
5
4
3
2
1
0
$1074 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 EVCNT1
$1075 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 EVCNT2
RESET: U
U
U
U
U
U
U
U
READ: Any time.
WRITE: Forces value to $00.
RESET: Indeterminate.
11-18
EVENT COUNTER
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