MC68HC11G5 Datasheet, PDF (151/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
SECTION 12
CPU, ADDRESSING MODES AND INSTRUCTION SET
This section discusses the M68HC11 central processing unit (CPU) architecture, its addressing
modes and the instruction set (by instruction type). Everything discussed in this section applies to
the MC68HC11G5. For more detailed information on the instruction set, refer to the M68HC11
Reference Manual (M68HC11RM/D).
12.1 PROGRAMMING MODEL AND CPU REGISTERS
In addition to being able to execute all M6800 and M6801 instructions, the MC68HC11G5 uses a
4-page opcode map to allow execution of 91 new opcodes (see 12.3: INSTRUCTION SET).
Seven registers, shown in Figure 12-1 and discussed in the following paragraphs, are available
to programmers.
7 Accumulator A 0 7 Accumulator B 0
15
Double Accumulator D
0
15
Index Register X
0
15
Index Register Y
0
15
Stack Pointer
0
15
Program Counter
0
7
0
Condition Code Register S X H I N Z V C
A:B
D
IX
IY
SP
PC
CCR
Carry
Overflow
Zero
Negative
I Interrupt Mask
Half-carry (from bit 3)
X Interrupt Mask
Stop Disable
Figure 12-1. Programming Model
CPU, ADDRESSING MODES AND INSTRUCTION SET
12-1
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