MC68HC11G5 Datasheet, PDF (89/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
6.4.20 Pulse Accumulator Control Register (PACTL)
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1
0
$1026
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PAEN PAMOD PEDGE I4/O5 RTR2 RTR1 RTR0 PACTL
RESET:
0
0
0
0
0
0
0
0
READ: Any time.
WRITE: Any time.
RESET: $00
PAEN — Pulse Accumulator System Enable
When PAEN is zero, the pulse accumulator counter is disabled from counting and the
PAIF and PAOVF flags cannot be set. The counter value and the states of the two flags
are not altered by the state of the PAEN bit (writing PAEN to zero does not clear them).
When PAEN is a one, the pulse accumulator counter and the setting mechanisms on the
two pulse accumulator flags PAIF and PAOVF are enabled.
0 – Pulse accumulator system disabled (no flags can become set and the counter is
stopped).
1 – Pulse accumulator system enabled
PAMOD — Pulse Accumulator Mode
The PAMOD control bit specifies “event” or “gated time accumulation” mode.
0 – Event counter mode.
1 – Gated time accumulation mode.
PEDGE — Pulse Accumulator Edge Control
The PEDGE bit is used to specify the active edge for the PAI input pin which is interpreted
as the trailing edge for the PAI gate enable input when the system is configured for gated
time accumulation.
PEDGE in Event Counter Mode (PAMOD = 0):
0 – Falling edges on PAI pin cause the count to be incremented.
1 – Rising edges on PAI pin cause the count to be incremented.
PEDGE in Gated Time Accumulation Mode (PAMOD = 1):
0 – PAI input pin high enables E divided by 64 clock to pulse accumulator and the
trailing falling edge on PAI sets the PAIF flag.
1 – PAI input pin low enables E divided by 64 clock to pulse accumulator and the
trailing rising edge on PAI sets the PAIF flag.
PROGRAMMABLE TIMER
6-19
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