MC68HC11G5 Datasheet, PDF (147/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
The following table applies to mode 0 only:
EVI2C
EVI2B
EVI2A
Clear input mode for EVCNT2
0
X
X
1
0
0
1
0
1
1
1
0
1
1
1
Not used
Falling edge of EVI2 (PH4)
Rising edge of EVI2 (PH4)
Logic HIGH (1) level on EVI2
Logic LOW (0) level on EVI2
In mode 0, EVI2 is used as a “clear” input to (EVCNT2).
Note: In mode 2, these three bits should be reset to zero to allow PH4 to be used as an I/O port.
EVI1C, EVI1B, EVI1A — Event Input Select 1 (EVI1)
These three bits determine the operation of event input unit 1 as shown in the following
table.
The following table applies to modes 0, 1 and 2 only:
EVI1C EVI1B EVI1A
PH5
Clock Source Count Mode
0
0
0
I/O
Count stop
0
0
1
I/O
Scaled E
Count always
0
1
0
EVI1
Scaled E
Inhibit counting on EVI1 = 0
0
1
1
EVI1
Scaled E
Inhibit counting on EVI1 = 1
1
0
0
EVI1
External
Count on falling edge of EVI1
1
0
1
EVI1
External
Count on rising edge of EVI1
1
1
X
EVI1
External
Count on both falling and
rising edges of EVI1
Note: In mode 3, these three bits should be reset to zero to allow PH5 to be used as an I/O port.
11.6.3 Counters Enable/Interrupt Mask Register (EVMSK)
7
6
5
4
3
2
1
0
$1072 EVCEN
EV2I EV1I EVMSK
RESET:
0
0
0
0
0
0
0
0
READ: Any time.
WRITE: Any time.
RESET: $00.
EVCEN — Event Counters Enable
0 – Event counters EVCNT1 and EVCNT2 are cleared. Also the event output (EVO)
is cleared to a logic low level (when EVPOL = 0 and EVOEN = 1). The EVCLK and
EVCTL registers should be written while this bit is “0”.
1 – Event counters are enabled.
EVENT COUNTER
11-17
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