MC68HC11G5 Datasheet, PDF (33/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
registers. Two special internal registers (INIT and CONFIG) require further explanation. The INIT
control register allows the RAM and internal register block to be repositioned in the memory map
during software initialization. The CONFIG control register controls the presence of ROM in the
memory map as well as the NOCOP watch-dog system enable.
3.5.1 RAM and I/O Mapping Register (INIT)
The INIT register is a special purpose 8-bit register that is used during initialization to change the
default locations of RAM and control registers within the MCU memory map. It can be written to only
once, within the first 64 E-clock cycles after a reset, and thereafter becomes a read-only register.
7
6
5
4
3
2
1
0
$103D RAM3 RAM2 RAM1 RAM0 REG3 REG2 REG1 REG0 INIT
RESET:
0
0
0
0
0
0
0
1
READ: Any time
WRITE: If SMOD = 0, may be written once only, and only during the first 64 cycles: after this time
the register becomes read-only. If SMOD = 1 (test or bootstrap mode), writes are always
permitted.
RAM3, RAM2, RAM1, RAM0 — Internal RAM map position
These four bits specify the four most significant bits of the 16-bit RAM address.
REG3, REG2, REG1, REG0 — Register block map position.
These four bits specify the four most significant bits of the 16-bit internal register space
address. For more details refer to the memory map.
Since the INIT register is set to $01 by reset, the default starting address is $0000 for RAM and $1000
for the 128 byte control and status register block. The upper four bits of the INIT register specify the
starting address for the 512 byte RAM, while the lower four bits specify the starting address for the
control and status register block. In each case, the four bits define the four most significant bits of
the 16-bit address.
If relocation conflicts occur between the RAM and the ROM, the RAM takes priority over the ROM
which simply becomes inaccessible at those locations. Similarly, if the control and status registers
are located so that they conflict with the RAM and/or ROM, the registers take priority and the RAM
and/or ROM at those locations become inaccessible. Also, if an internal resource conflicts with an
external device, no harmful conflict occurs. (Data from the external device is not applied to the
internal data bus, thus it cannot interfere with the internal read.)
MEMORY AND CONTROL/STATUS REGISTERS
3-5
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