MC68HC11G5 Datasheet, PDF (162/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
The XIRQ interrupt mask (X) bit is another unusual case. The definition of this bit specifically states
that software shall not be allowed to change X from 0 to 1, in fact, this is even prohibited by hardware
logic. This immediately eliminates a need for a set X instruction. For arguments similar to those used
for the S bit, the TAP instruction is preferred over a clear X instruction as a means of clearing X
because TAP makes it a little less likely that X will become cleared before the programmer really
intended to clear it.
The half-carry (H) bit needs no set or clear instructions because this condition code bit is only used
by the DAA instruction to adjust the result of a BCD add or subtract. The H bit is not used as a test
condition for any branches so it would not be useful to be able to set or clear this bit.
This leaves only the negative (N) and zero (Z) condition code bits. In contrast to S, X, and H, it is
often useful to be able to easily set or clear these flag bits. A clear accumulator instruction such as
CLRB will clear both the N and Z condition code bits. The instruction “LDAA #$80” causes both N
and Z to be set. Since there are so many simple instructions that can accomplish setting or clearing
of N and Z, it is not necessary to provide specific set and clear instructions for N and Z in this group.
12.3.4 Program Control Instructions
This group of instructions is used to control the flow of a program rather than to manipulate data.
Since this group is so large it has been further divided into five subgroups:
1. Branches,
2. Jumps,
3. Subroutine calls and returns,
4. Interrupt handling,
5. Miscellaneous.
12.3.4.1
Branches
These instructions allow the CPU to make decisions based on the contents of the condition code
bits. All decision blocks in a flow chart would correspond to one of the conditional branch instructions
which are summarized in the following table.
12-12
CPU, ADDRESSING MODES AND INSTRUCTION SET
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