MC68HC11G5 Datasheet, PDF (157/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
12.3.1.3
Multiply and Divide
One multiply and two divide instructions are provided. The 8-bit by 8-bit multiply instruction (MUL)
produces a 16-bit result. The integer divide (IDIV) performs a 16-bit by 16-bit divide and produces
a 16-bit result and a 16-bit remainder. The fractional divide (FDIV) divides a 16-bit numerator by a
larger 16-bit denominator to produce a 16-bit result (a binary weighted fraction between 0 and
0.99998) and a 16-bit remainder. FDIV can be used to further resolve the remainder from an IDIV
or FDIV operation.
Table 12-3. Multiply and Divide
Function
Mnemonic INH
Multiply (A x B D)
MUL
X
Fractional Divide (D ÷ X X; r D)
FDIV
X
Integer Divide (D ÷ X X; r D)
IDIV
X
12.3.1.4
Logical Operations
This group of instructions is used to perform the boolean logical operations AND, inclusive-OR,
exclusive-OR, and complement.
Table 12-4. Logical Operations
Function
AND A with Memory
AND B with Memory
Bit(s) Test A with Memory
Bit(s) Test B with Memory
Ones Complement Memory Byte
Ones Complement A
Ones Complement B
OR A with Memory (Exclusive
OR B with Memory (Exclusive
OR A with Memory (Inclusive)
OR B with Memory (Inclusive)
Mnemonic IMM DIR EXT INDX INDY INH
ANDA
X
X
X
X
X
ANDB
X
X
X
X
X
BITA
X
X
X
X
X
BITB
X
X
X
X
X
COM
X
X
X
COMA
X
COMB
X
EORA
X
X
X
X
X
EORB
X
X
X
X
X
ORAA
X
X
X
X
X
ORAB
X
X
X
X
X
CPU, ADDRESSING MODES AND INSTRUCTION SET
12-7
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