MC68HC11G5 Datasheet, PDF (173/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
13.5 CONTROL TIMING
(VDD = 5.0 Vdc ± 10%, V _SS = 0 Vdc, TA = TL to TH unless otherwise noted)
Characteristic
Symbol
Min
Max
External Oscillator Frequency
Crystal option fXTAL
—
8.4
External clock option
4fo
DC
8.4
Internal Operating Frequency
Cycle Time
Crystal Oscillator Startup Time
Crystal (f _XTAL/4)
fo
External clock
fo
—
2.1
DC
2.1
All outputs except XTAL tcyc
476
—
tOXOV
—
100
Stop Recovery Startup Time
DLY = 0
DLY = 1
Wait Recovery Startup Time
Reset Input Pulse Width (See Note 1)
(To guarantee external reset vector)
(Minimum input time; may be pre-empted by internal reset)
tSRS
tSRS
tWRS
tRLRH
—
4
—
4064
—
4
8
—
1
—
Mode Programming
Interrupt Pulse Width,
IRQ Edge Sensitive Mode
Setup time tMPS
2
—
Hold time tMPH
0
—
tILIH = tcyc + 20ns tILIH
496
—
Interrupt Pulse Period
tILIL
Note 2 —
Processor Control
RESET, WAIT, IRQ
MRDY
HALT
Bus Tri State Enable
Bus Tri State Disable
(tPCS = 1/4 tcyc - 50ns)
(tPCS = 1/4 tcyc + 20ns)
(tTSE = 1/4 tcyc + 40ns)
tPCS
tPCS
tPCS
tTSE
tTSD
69
—
50
—
170
—
—
159
—
65
NOTES:
1. RESET will be recognised during the first clock cycle it is held low. Internal circuitry then drives
the pin low for four clock cycles, releases the pin, and samples the pin level two cycles later to
determine the source of the interrupt.
2. The minimum period t _ILILshould not be less than the number of cycles it takes to execute the
interrupt service routine plus 21 t _cyc .
3. All timing is shown with respect to 20% V _DD and 70% VDD unless otherwise noted.
Unit
MHz
MHZ
MHz
MHZ
ns
ms
tcyc
tcyc
tcyc
tcyc
tcyc
ns
ns
tcyc
ns
ns
ns
ns
ns
ELECTRICAL SPECIFICATIONS
13-7
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