MC68HC11G5 Datasheet, PDF (88/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
PAIF — Pulse Accumulator Input Edge Flag
Set when the selected edge is detected at the PAI input pin. In event mode the event edge
triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal
at the PAI input pin triggers PAIF. This bit is cleared by writing to the TFLG2 register with
bit 4 set.
TO2F — Timer Overflow 2 Flag
Set when 16-bit free-running timer 2 overflows from $FFFF to $0000. This bit is cleared
by writing to the TFLG2 register with bit 3 set.
5/6F — Input Capture 5/Output Compare 6 Flag
Set by input capture IC5 or output compare OC6, depending on which function is
selected. This bit is cleared by writing to the TFLG2 register with bit 2 set.
6/7F — Input Capture 6/Output Compare 7 Flag
Set by input capture IC6 or output compare OC7, depending on which function is
selected. This bit is cleared by writing to the TFLG2 register with bit 1 set.
6.4.19 Count Register (PACNT)
PACNT is a read/write 8-bit counter register which is not initialized by reset. The PACTL register
contains four control bits which enable and configure the pulse accumulator system. The pulse
accumulator uses Port A bit 7 as its PAI input but this pin can also serve as a general purpose I/O
pin and as the timer output compare OC1 output.
7
6
5
4
3
2
1
0
$1027 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 PACNT
RESET: U
U
U
U
U
U
U
U
READ: Any time (returns count from pulse accumulator counter).
WRITE: Any time.
RESET: Indeterminate.
6-18
PROGRAMMABLE TIMER
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