MC68HC11G5 Datasheet, PDF (52/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
IRV — Internal Read Visibility
READ: Any time.
WRITE: If SMOD=1, any time. If SMOD=0, only one write is allowed.
RESET: Test and bootstrap modes – 1; single chip and expanded modes – 0.
0 – No visibility of internal reads on external bus.
1 – Data from internal reads is driven out on the external data bus.
MRDY — Memory Ready Enable
READ: Any time.
WRITE: Any time.
0 – Memory Ready is disabled, Port H bit 7 is general purpose I/O.
1 – Memory Ready is enabled, Port H bit 7 is forced to be an input used as the MRDY
line. External bus accesses will be stretched as long as this line is held low.
NHALT — Enable Halt Function
READ: Any time
WRITE: Any time
0 – Halt enabled (a logic low level detected on the HALT pin will cause the part to go
into the HALT state at the completion of the present instruction).
1 – Halt disabled.
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INPUT/OUTPUT PORTS
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