MC68HC11G5 Datasheet, PDF (62/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
All interrupt sources from on-chip peripherals have software programmable interrupt mask bits
which may be used to selectively inhibit automatic hardware response to each interrupt source. In
addition the X and I bits in the condition code register act as class inhibit masks to inhibit all sources
in the X bit and/or I bit class. Figures 5-2, 5-3 and 5-4 summarize the priority structure and additional
mask conditions that lead to the recognition of interrupt requests in the MC68HC11G5.
POWER-ON RESET
(POR)
DELAY 4064 E CYCLES
HIGHEST
EXTERNAL RESET
PRIORITY
CLOCK MONITOR FAIL
(WITH CME = 1)
LOAD PROGRAM COUNTER
WITH CONTENTS OF
$FFFE, FFFF (VECTOR FETCH)
LOAD PROGRAM COUNTER
WITH CONTENTS OF
$FFFC, FFFD (VECTOR FETCH)
LOWEST
COP WATCHDOG
TIMEOUT
(WITH NOCOP = 0)
LOAD PROGRAM COUNTER
WITH CONTENTS OF
$FFFA, FFFB (VECTOR FETCH)
5-10
SET S, X, AND I BITS
IN CCR
RESET MCU
HARDWARE
1A
BEGIN AN INSTRUCTION
SEQUENCE
YES
X BIT
IN CCR
SET ?
NO
XIRQ PIN
YES
LOW ?
NO
STACK CPU
REGISTERS
SET X AND I BITS
FETCH VECTOR
$FFF4, FFF5
1B
Figure 5-2. Processing Flow out of Resets
RESETS, INTERRUPTS AND LOW POWER MODES
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