MC68HC11G5 Datasheet, PDF (54/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
5.1.3 Computer Operating Properly (COP) Reset
The MCU contains a watchdog timer which automatically times out unless it is reset within a specific
time by a program reset sequence. If the COP watchdog timer is allowed to timeout, a reset is
generated which drives the RESET pin low to reset the MCU and the external system.
The COP reset function can be enabled by programming the NOCOP control bit in the system
configuration register (CONFIG). Once programmed, this control bit remains set (or cleared), even
when no power is applied, and the COP function is enabled or disabled independent of resident
software. Protected control bits CR0 and CR1 in the configuration options register (OPTION) allow
the user to select one of four COP timeout periods. Table 5-1 shows the relationship between CR0
and CR1 and the timeout period for various system clock frequencies.
Table 5-1. COP Timeout Periods
CR1
CR0
E ÷ 2 ¹⁵
Divided
By
XTAL = 2²³ XTAL = 8.0 MHz
Timeout
Timeout
– 0 / +15.6 ms – 0 / +16.4 ms
XTAL =
4.9152 MHz
Timeout
– 0 / +26.7 ms
XTAL = 4.0 MHz
Timeout
– 0 / +32.8 ms
XTAL =
3.6864 MHz
Timeout
– 0 / +35.6 ms
00
1
15.625 ms
16.384 ms
26.667 ms
32.768 ms
35.556 ms
01
4
62.5 ms
65.536 ms
106.67 ms
131.07 ms
142.22 ms
10
16
250 ms
262.14 ms
426.67 ms
524.29 ms
568.89 ms
11
64
1s
1.049 s
1.707 s
2.1 s
2.276 s
E=
2.1 MHz
2.0 MHz
1.2288 MHz
1.0 MHz
921.6 kHz
The sequence for resetting the watchdog timer is as follows:
1) Write $55 to the COP reset register (COPRST)
2) Write $AA to the COP reset register (COPRST)
Both writes must occur in this sequence prior to the timeout, but any number of instructions can be
executed between the two writes.
5.1.4 Clock Monitor Reset
The MCU contains a clock monitor circuit which measures the E-clock frequency. The clock monitor
function is enabled by the CME control bit in the OPTION register. Upon detection of a slow or absent
clock, the clock monitor circuit (if enabled by CME = 1) will cause a system reset to be generated.
If the E-clock input rate is above approximately 200 kHz, then the clock monitor does not generate
a reset. If the E-clock is lost or its frequency falls below 10 kHz, then a reset is generated, and the
RESET pin is driven low to reset the external system.
RESETS, INTERRUPTS AND LOW POWER MODES
5-2
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