MC68HC11G5 Datasheet, PDF (135/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
the value Y in ECMP1A, the event output (EVO) will always be low (when EVPOL = 0). Note that
this skew value should be a smaller value than the minimum value of the pulse width Y. (If the value
in this register is larger than the value Y in ECMP1A, it is possible to miss a pulse in one cycle and
the following cycle will be reversed in polarity cycle, which is equivalent to exchanging X’ and Y in
Figure 11-2.).
11.2.2.4
Counter 2 (EVCNT2)
This counter is cleared by the external signal on the EVI2 pin. The source chosen by input selector
INPUT1 is used as the clock input to both counters (EVCNT1 and EVCNT2). This counter is used
to control the amount of phase shift between the external signal’s active edge and the start of the
PWM output signal, using ECMP2A. A successful compare with compare register 2B will cause an
interrupt request 2 (EVENT2) to be generated.
11.2.2.5
Compare Register 2A (ECMP2A); (X)
This compare register holds the value of the phase shift between the external signal active edge (or
level) and the PWM output signal. Note that this phase shift value is added to the skew value held
in ECMP1B to determine the timing of the leading edge of the PWM output pulse. If the value in this
register is zero, then the active edge of the external signal on EVI2 will reset EVCNT1 immediately
and there will be no phase shift, only skew.
11.2.2.6
Compare Register 2B (ECMP2B)
This compare register can be used to generate an interrupt when the PA unit has accumulated a
desired number of clock pulses. When a match occurs between EVCNT2 and ECMP2B, an interrupt
signal EVENT2 is generated which, if enabled, will interrupt the CPU.
11.2.2.7
Input Unit 1 (EVI1)
This unit selects the clock source for EVCNT1 and EVCNT2. If the input signal on the EVI1 pin (PH5)
is used as a clock source, this unit will select the rising edge, falling edge or both edges of the input
signal. If the E-clock or a scaled E-clock is selected as the clock source, this unit controls the active
gated input level which inhibits counting. Even if PH5 is used for general purpose I/O, this unit is able
to select the pass mode (EVI1C = 0, EVI1B = 0, EVI1A = 1).
11.2.2.8
Input Unit 2 (EVI2)
This unit selects the active edge or level of the input signal on the EVI2 pin (PH4) which will reset
EVCNT2 (to zero).
11.2.2.9
Output Unit (EVO)
This unit controls the polarity of the PWM output signal. With the EVOEN (Event Output Enable) bit
in the EVCTL register set to one, the EVPOL (Event Output Polarity) bit determines the polarity of
the PWM output.
EVENT COUNTER
11-5
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