MC68HC11G5 Datasheet, PDF (164/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
12.3.4.2
Jumps
The jump instruction allows control to be passed to any address in the 64 kbyte memory map.
Jump
Function
Table 12-10. Jumps
Mnemonic DIR
JMP
X
EXT INDX INDY INH
X
X
X
12.3.4.3
Subroutine Calls and Returns (BSR, JSR, RTS)
These instructions provide an easy way to break a programming task into manageable blocks called
subroutines. The CPU automates the process of remembering the address in the main program
where processing should resume after the subroutine is finished. This address is automatically
pushed onto the stack when the subroutine is called and is pulled off the stack during the return from
subroutine (RTS) instruction which ends the subroutine.
Table 12-11. Subroutine Calls and Returns (BSR, JSR, RTS)
Function
Branch to Subroutine
Jump to Subroutine
Return from Subroutine
Mnemonic REL DIR EXT INDX INDY INH
BSR
X
JSR
X
X
X
X
RTS
X
12.3.4.4
Interrupt Handling (RTI, SWI, WAI)
This group of instructions is related to interrupt operations.
Table 12-12. Interrupt Handling (RTI, SWI, WAI)
Function
Return from Interrupt
Software Interrupt
Wait for Interrupt
Mnemonic INH
RTI
X
SWI
X
WAI
X
The software interrupt (SWI) instruction is similar to a jump to subroutine (JSR) instruction except
that the contents of all working CPU registers are saved on the stack, rather than just saving the
return address. SWI is unusual in that it is requested by the software program as opposed to other
interrupts which are requested asynchronously with respect to the executing program.
12-14
CPU, ADDRESSING MODES AND INSTRUCTION SET
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