MC68HC11G5 Datasheet, PDF (113/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
SECTION 9
ANALOG-TO-DIGITAL CONVERTER
The Analog to Digital converter system consists of a single 10-bit successive approximation type
converter and a 16-channel multiplexer. Eight of the channels are connected to pins on the
MC68HC11G5, four are unused and the remaining four channels are dedicated to internal reference
points or test functions. There are eight 10-bit result registers and control logic allows for four or eight
consecutive conversions before stopping or for conversions to continue with the newest conversion
overwriting the oldest result register. Also, the control logic allows conversions to be performed on
a single selected channel, multiple times or consecutively on a selected group of four channels. In
addition, the control logic allows for converting all eight channels and either stopping or converting
continuously.
Two dedicated lines (V_rl and V_rh) are provided for the reference voltage inputs. These pins may be
connected to a separate or isolated power supply to ensure full accuracy of the AD conversion.
The 10-bit A/D converter accepts analog inputs ranging from V_rl to V_rh. Smaller input ranges can
also be obtained by adjusting V_rl and V_rh to the desired upper and lower limits. Conversion is
specified and tested for V_rl = 0 volts and V_rh = 5 volts. The A/D system can be operated with V_rh below
V_DD and/or V_rl above V_SS as long as V_rh is above V_rl by enough to support the conversions (2.5
to 5.0 volts).
Each set of four conversions takes 144 cycles of the E-clock, provided that E is greater than or equal
to 750 kHz. If E is less than 750 kHz, an internal R-C oscillator, which is nominally 1.5 MHz, must
be used for the A/D conversion clock. When the internal R-C oscillator is being used as the
conversion clock, the conversion complete flag (CCF) must be used to determine when a conversion
sequence has been completed. When using the internal R-C oscillator for A/D conversions the
sample and conversion process runs at the nominal 1.5 MHz rate; however, the conversion results
must be transferred to the MCU result registers synchronously with the MCU E-clock, so conversion
time is limited to a maximum of one channel per E-clock cycle.
Two control bits in the OPTION register control the basic configuration of the A/D system. The A to D
power-up bit (ADPU) allows the system to be disabled, resulting in reduced power consumption
when the A/D system is not being used. Any conversion which is in process when ADPU is written
to zero will be aborted. A delay of typically 100 microseconds is required after turning on the A/D
(by writing ADPU from 0 to 1) for the analog and comparator sections to stabilize. The CSEL bit is
used to select either the internal R-C oscillator or the MCU E-clock as the A/D system clock source.
ANALOG-TO-DIGITAL CONVERTER
9-1
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