MC68HC11G5 Datasheet, PDF (126/195 Pages) Motorola, Inc – High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller

Freescale Semiconductor, Inc.
Note:
If the duty register is greater than or equal to the value in the period register there will be
no duty change in state. In addition, if the duty register is set to $00 the output will always
be in the state which would normally be the state changed to at the duty change of state.
Refer to the “Boundary Cases” section for more information on this.
7
6
5
4
3
2
1
0
$106C BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 PWDTY1
$106D BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 PWDTY2
$106E BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 PWDTY3
$106F BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 PWDTY4
READ: Any time.
WRITE: Any time.
RESET: $FF.
10.5.4 Clock Select Register (PWCLK)
7
6
5
4
3
2
1
0
$1060 CON34 CON12 PCKA2 PCKA1 0 PCKB3 PCKB2 PCKB1 PWCLK
RESET:
0
0
0
0
0
0
0
0
READ: Any time.
WRITE: Any time.
RESET: $00.
CON34 — Concatenate channels 3 and 4
1 – Channels 3 and 4 are concatenated to create one 16-bit PWM channel. (Channel
3 becomes the high order byte and channel 4 becomes the low order byte. The
channel 4 output is used as the output for this 16-bit PWM (bit 3 of Port H)).
0 – Channels 3 and 4 are separate 8-bit PWM channels.
10-6
PULSE WIDTH MODULATION TIMER
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