AMIC110 Datasheet, PDF (95/214 Pages) Texas Instruments – Sitara Processors

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AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
6.1.4 Digital Phase-Locked Loop Power Supply Requirements
NOTE
The LCD module is not supported for this family of devices, but the "LCD" name is still
present in some supply voltage or PLL names.
The digital phase-locked loop (DPLL) provides all interface clocks and functional clocks to the processor
of the AMIC110 device. The AMIC110 device integrates five different DPLLs—Core DPLL, Per DPLL, LCD
DPLL, DDR DPLL, MPU DPLL.
Figure 6-8 shows the power supply connectivity implemented in the AMIC110 device. Table 6-1 provides
the power supply requirements for the DPLL.
VDDS_PLL_MPU
VDDS_PLL_CORE_LCD
MPU
PLL
CORE
PLL
LCD
PLL
PER
PLL
DDR
PLL
VDDA1P8V_USB0
VDDS_PLL_DDR
Figure 6-8. DPLL Power Supply Connectivity
SUPPLY NAME
VDDA1P8V_USB0
VDDS_PLL_MPU
VDDS_PLL_CORE_LCD
VDDS_PLL_DDR
Table 6-1. DPLL Power Supply Requirements
DESCRIPTION
Supply voltage range for USBPHY and PER DPLL, Analog, 1.8 V
Max peak-to-peak supply noise
Supply voltage range for DPLL MPU, analog
Max peak-to-peak supply noise
Supply voltage range for DPLL CORE and LCD, analog
Max peak-to-peak supply noise
Supply voltage range for DPLL DDR, analog
Max peak-to-peak supply noise
MIN NOM MAX UNIT
1.71 1.8 1.89 V
50 mV (p-p)
1.71 1.8 1.89 V
50 mV (p-p)
1.71 1.8 1.89 V
50 mV (p-p)
1.71 1.8 1.89 V
50 mV (p-p)
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Power and Clocking
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