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AMIC110 Datasheet, PDF (119/214 Pages) Texas Instruments – Sitara Processors
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AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
7.7.1.2 GPMC and NOR Flash—Asynchronous Mode
Table 7-9 and Table 7-10 assume testing over the recommended operating conditions and electrical
characteristic conditions shown in Table 7-8 (see Figure 7-8 through Figure 7-13).
Table 7-8. GPMC and NOR Flash Timing Conditions—Asynchronous Mode
Input Conditions
tR
Input signal rise time
tF
Input signal fall time
Output Condition
CLOAD
Output load capacitance
MIN
TYP
1
1
3
MAX
5
5
30
UNIT
ns
ns
pF
Table 7-9. GPMC and NOR Flash Internal Timing Requirements—Asynchronous Mode(1)(2)
OPP100
OPP50
NO.
MIN MAX
MIN MAX
FI1
Delay time, output data gpmc_ad[15:0] generation from internal functional clock
GPMC_FCLK(3)
6.5
6.5
FI2
Delay time, input data gpmc_ad[15:0] capture from internal functional clock
GPMC_FCLK(3)
4
4
FI3
Delay time, output chip select gpmc_csn[x] generation from internal functional
clock GPMC_FCLK(3)
6.5
6.5
FI4
Delay time, output address gpmc_a[27:1] generation from internal functional clock
GPMC_FCLK(3)
6.5
6.5
FI5
Delay time, output address gpmc_a[27:1] valid from internal functional clock
GPMC_FCLK(3)
6.5
6.5
Delay time, output lower-byte enable and command latch enable gpmc_be0n_cle,
FI6 output upper-byte enable gpmc_be1n generation from internal functional clock
GPMC_FCLK(3)
6.5
6.5
FI7
Delay time, output enable gpmc_oen generation from internal functional clock
GPMC_FCLK(3)
6.5
6.5
FI8
Delay time, output write enable gpmc_wen generation from internal functional
clock GPMC_FCLK(3)
FI9 Skew, internal functional clock GPMC_FCLK(3)
6.5
6.5
100
100
(1) The internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field.
(2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally.
(3) GPMC_FCLK is general-purpose memory controller internal functional clock.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ps
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