AMIC110 Datasheet, PDF (155/214 Pages) Texas Instruments – Sitara Processors

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AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
7.7.2.3.3.1 DDR3 Interface Schematic
The DDR3 interface schematic varies, depending upon the width of the DDR3 devices used. Figure 7-33
shows the schematic connections for 16-bit interface on the AMIC110 device using one x16 DDR3 device
and Figure 7-35 shows the schematic connections for 16-bit interface on the AMIC110 device using two
x8 DDR3 devices. The AMIC110 DDR3 memory interface only supports 16-bit wide mode of operation.
The AMIC110 device can only source one load connected to the DQS[x] and DQ[x] net class signals and
two loads connected to the CK and ADDR_CTRL net class signals. For more information related to net
classes, see Section 7.7.2.3.3.8.
AMIC110
16-Bit DDR3
Interface
DDR_D15
8
DDR_D8
DDR_DQM1
DDR_DQS1
DDR_DQSn1
DDR_D7
8
DDR_D0
DDR_DQM0
DDR_DQS0
DDR_DQSn0
DDR_CK
DDR_CKn
DDR_ODT
DDR_CSn0
DDR_BA0
DDR_BA1
DDR_BA2
DDR_A0
15
DDR_A15
DDR_CASn
DDR_RASn
DDR_WEn
DDR_CKE
DDR_RESETn
DDR_VREF
0.1 µF
16-Bit DDR3
Device
DQU7
DQU0
DMU
DQSU
DQSU#
DQL7
DQL0
DML
DQSL
DQSL#
CK
CK#
ODT
CS#
BA0
BA1
BA2
A0
A15
CAS#
RAS#
WE#
CKE
RESET#
ZQ
ZQ
VREFDQ
VREFCA
0.1 µF
Zo ^{0.1 µF}
VDDS_DDR
Zo
DDR_VTT
Zo
Zo
DDR_VREF
0.1 µF
DDR_VTP
49.9 Ω
(±1%, 20 mW)
Zo
Termination is required. See terminator comments.
ZQ
Value determined according to the DDR3 memory device data sheet.
Copyright © 2016, Texas Instruments Incorporated
Figure 7-33. 16-Bit DDR3 Interface Using One 16-Bit DDR3 Device with V_TT Termination
Copyright © 2016, Texas Instruments Incorporated
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Peripheral Information and Timings 155