AMIC110 Datasheet, PDF (198/214 Pages) Texas Instruments – Sitara Processors

AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
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(see Figure 7-81)
NO.
1
t_{c(TX_CLK)}
2
t_{w(TX_CLKH)}
3
t_{w(TX_CLKL)}
4
t_{t(TX_CLK)}
Table 7-89. PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
Cycle time, TX_CLK
Pulse duration, TX_CLK high
Pulse duration, TX_CLK low
Transition time, TX_CLK
MIN
399.96
140
140
10 Mbps
TYP
1
2
MAX
400.04
260
260
3
100 Mbps
MIN
TYP
39.996
14
14
MAX
40.004
26
26
3
4
3
UNIT
ns
ns
ns
ns
MII_TXCLK
4
Figure 7-81. PRU-ICSS MII_TXCLK Timing
Table 7-90. PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
(see Figure 7-82)
10 Mbps
100 Mbps
NO.
UNIT
MIN TYP MAX MIN TYP MAX
t_{su(RXD-RX_CLK)}
Setup time, RXD[3:0] valid before RX_CLK
1 t_{su(RX_DV-RX_CLK)} Setup time, RX_DV valid before RX_CLK
8
t_{su(RX_ER-RX_CLK)} Setup time, RX_ER valid before RX_CLK
t_{h(RX_CLK-RXD)}
Hold time RXD[3:0] valid after RX_CLK
2 t_{h(RX_CLK-RX_DV)} Hold time RX_DV valid after RX_CLK
8
t_{h(RX_CLK-RX_ER)} Hold time RX_ER valid after RX_CLK
8
ns
8
ns
1
2
MII_MRCLK (Input)
MII_RXD[3:0],
MII_RXDV,
MII_RXER (Inputs)
Figure 7-82. PRU-ICSS MII_RXD[3:0], MII_RXDV, and MII_RXER Timing
198 Peripheral Information and Timings
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