AMIC110 Datasheet, PDF (186/214 Pages) Texas Instruments – Sitara Processors

AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
(4) Case P = 20.8 ns, A = (TCS + 1) × TSPICLKREF (TCS is a bit field of MCSPI_CH(i)CONF register).
Case P > 20.8 ns, A = (TCS + 0.5) × Fratio × TSPICLKREF (TCS is a bit field of MCSPI_CH(i)CONF register).
Note: P = SPI_CLK clock period.
(5) B = (TCS + 0.5) × TSPICLKREF × Fratio (TCS is a bit field of MCSPI_CH(i)CONF register, Fratio: Even ≥ 2).
SPI_CS[x] (Out)
PHA=0
EPOL=1
SPI_SCLK (Out) ^POL=0
SPI_SCLK (Out)
POL=1
SPI_D[x] (SOMI, In)
1
3
8
2
9
1
2
3
4
5
Bit n-1
4
5
Bit n-2
Bit n-3
Bit n-4
Bit 0
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SPI_CS[x] (Out)
PHA=1
EPOL=1
SPI_SCLK (Out) ^POL=0
SPI_SCLK (Out)
POL=1
SPI_D[x] (SOMI, In)
1
3
8
2
1
2
3
4
5
Bit n-1
4
5
Bit n-2
Bit n-3
Bit 1
Figure 7-61. SPI Master Mode Receive Timing
9
Bit 0
186 Peripheral Information and Timings
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