AMIC110 Datasheet, PDF (181/214 Pages) Texas Instruments – Sitara Processors

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McASP[x]_ACLKR/X (Falling Edge Polarity)
McASP[x]_AHCLKR/X (Rising Edge Polarity)
McASP[x]_ACLKR/X (CLKRP = CLKXP = 1)^(A)
McASP[x]_ACLKR/X (CLKRP = CLKXP = 0)^(B)
McASP[x]_AFSR/X (Bit Width, 0 Bit Delay)
McASP[x]_AFSR/X (Bit Width, 1 Bit Delay)
McASP[x]_AFSR/X (Bit Width, 2 Bit Delay)
McASP[x]_AFSR/X (Slot Width, 0 Bit Delay)
McASP[x]_AFSR/X (Slot Width, 1 Bit Delay)
McASP[x]_AFSR/X (Slot Width, 2 Bit Delay)
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AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
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McASP[x]_AXR[x] (Data Out/Transmit)
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A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
Figure 7-58. McASP Output Timing
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Peripheral Information and Timings 181