AMIC110 Datasheet, PDF (185/214 Pages) Texas Instruments – Sitara Processors

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AMIC110
SPRS971A – AUGUST 2016 – REVISED SEPTEMBER 2016
7.12.1.2 McSPI—Master Mode
Table 7-64. McSPI Timing Conditions – Master Mode
PARAMETER
Input Conditions
t_r
Input signal rise time
t_f
Input signal fall time
Output Condition
C_load
Output load capacitance
LOW LOAD
MIN
MAX
8
8
5
HIGH LOAD
UNIT
MIN
MAX
8 ns
8 ns
25 pF
Table 7-65. Timing Requirements for McSPI Input Timings – Master Mode
(see Figure 7-61)
OPP100
OPP50
NO.
LOW LOAD
HIGH LOAD
LOW LOAD
HIGH LOAD
MIN MAX MIN MAX MIN MAX MIN MAX
4
t_su(SOMI-
SPICLKH)
Setup time, SPI_D[x] (SOMI) valid before
SPI_CLK active edge⁽¹⁾
Industrial extended
5
t_h(SPICLKH-
Hold time, SPI_D[x]
(SOMI) valid after
temperature
(-40°C to 125°C)
SOMI)
SPI_CLK active edge⁽¹⁾
All other
temperature ranges
2.29
7.1
4.7
3.02
7.1
4.7
2.29
7.1
4.7
3.02
7.1
4.7
(1) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.
UNIT
ns
ns
Table 7-66. Switching Characteristics for McSPI Output Timings – Master Mode
(see Figure 7-62)
NO.
PARAMETER
1
t_c(SPICLK)
2
t_w(SPICLKL)
Cycle time, SPI_CLK
Typical pulse duration,
SPI_CLK low
t_w(SPICLKH)
3
t_r(SPICLK)
Typical pulse duration,
SPI_CLK high
Rising time, SPI_CLK
t_f(SPICLK)
Falling time, SPI_CLK
Delay time, SPI_CLK
6 t_{d(SPICLK-SIMO)} active edge to SPI_D[x]
(SIMO) transition⁽²⁾
7
t_d(CS-SIMO)
Delay time, SPI_CS active
edge to SPI_D[x] (SIMO)
transition⁽²⁾
8
t_d(CS-SPICLK)
Delay time,
SPI_CS active
to SPI_CLK
first edge
Mode 1
and 3⁽³⁾
Mode 0
and 2⁽³⁾
9
t_d(SPICLK-CS)
Delay time,
SPI_CLK last
edge to
SPI_CS
inactive
Mode 1
and 3⁽³⁾
Mode 0
and 2⁽³⁾
OPP100
LOW LOAD
HIGH LOAD
MIN
MAX
MIN
MAX
20.8
20.8
0.5P –
1.04⁽¹⁾
0.5P +
1.04⁽¹⁾
0.5P –
2.08⁽¹⁾
0.5P +
2.08⁽¹⁾
0.5P –
1.04⁽¹⁾
0.5P +
1.04⁽¹⁾
0.5P –
2.08⁽¹⁾
0.5P +
2.08⁽¹⁾
3.82
3.82
3.44
3.44
–3.57
3.57
–4.62
4.62
OPP50
LOW LOAD
HIGH LOAD
UNIT
MIN
MAX
MIN
MAX
41.6
41.6
ns
0.5P –
1.04⁽¹⁾
0.5P +
1.04⁽¹⁾
0.5P –
2.08⁽¹⁾
0.5P +
2.08⁽¹⁾
ns
0.5P –
1.04⁽¹⁾
0.5P +
1.04⁽¹⁾
0.5P –
2.08⁽¹⁾
0.5P +
2.08⁽¹⁾
ns
3.82
3.82 ns
3.44
3.44 ns
–3.57
3.57
–4.62
4.62 ns
A – 4.2⁽⁴⁾
B – 4.2⁽⁵⁾
B – 4.2⁽⁵⁾
A – 4.2⁽⁴⁾
3.57
A – 2.54⁽⁴⁾
B – 2.54⁽⁵⁾
B – 2.54⁽⁵⁾
A – 2.54⁽⁴⁾
4.62
A – 4.2⁽⁴⁾
B – 4.2⁽⁵⁾
B – 4.2⁽⁵⁾
A – 4.2⁽⁴⁾
3.57
A – 2.54⁽⁴⁾
B – 2.54⁽⁵⁾
B – 2.54⁽⁵⁾
A – 2.54⁽⁴⁾
4.62 ns
ns
ns
ns
ns
(1) P = SPI_CLK period.
(2) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.
(3) The polarity of SPIx_CLK and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all
software configurable:
– SPIx_CLK(1) phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 1 (Modes 1 and 3).
– SPIx_CLK(1) phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 0 (Modes 0 and 2).
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